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| Preliminary Technical Data FEATURES 2 A, Low Dropout, CMOS Linear Regulator ADP1740/ADP1741 TYPICAL APPLICATION CIRCUITS VIN = 1.8V 4.7F VOUT = 1.5V 4.7F Maximum output current: 2 A Input voltage range: 1.6 V to 3.6 V Low shutdown current: <1 A Low dropout voltage: 200 mV @ 2 A load Initial accuracy: 1% Accuracy over line, load, and temperature: 2.5% 7 fixed output voltage options with soft start (ADP1740): 0.75 V to 2.5 V Adjustable output voltage options with soft start (ADP1741): 0.75 V to 3.0 V Stable with small 4.7 F ceramic output capacitor Excellent load/line transient response Current limit and thermal overload protection Power Good indicator Logic-controlled enable 16 IN 1 IN 100k 2 IN 3 IN 4 EN 15 IN 13 14 OUT OUT OUT 12 OUT 11 PIN 1 INDICATOR ADP1740 TOP VIEW OUT 10 (Not to Scale) SENSE 9 PG 5 GND SS 7 6 NC 8 10nF NC = NO CONNECT Figure 1. ADP1740 with Fixed Output Voltage, 1.5 V APPLICATIONS Notebook computers Memory components Telecommunications equipment Network equipment DSP/FPGA/microprocessor supplies Instrumentation equipment/data acquisition systems VIN = 1.8V 4.7F VOUT = 0.5V(1 + R1/R2) 4.7F 16 IN 1 IN 100k 2 IN 3 IN 4 EN 15 IN 13 14 OUT OUT OUT 12 OUT 11 R1 PIN 1 INDICATOR ADP1741 TOP VIEW OUT 10 (Not to Scale) ADJ 9 PG 5 GND SS 7 6 NC 8 10nF R2 07081-002 NC = NO CONNECT Figure 2. ADP1741 with Adjustable Output Voltage, 0.75 V to 3.0 V GENERAL DESCRIPTION The ADP1740/ADP1741 are CMOS, low dropout linear regulators that operate from 1.6 V to 3.6 V and provide up to 2 A of output current. Using an advanced proprietary architecture, they provide high power supply rejection and achieve excellent line and load transient response with a small 4.7 F ceramic output capacitor. The ADP1740 is available in seven fixed output voltage options. The ADP1741 is an adjustable output voltage version, which allows output voltages that range from 0.75 V to 3.0 V via an external divider. The ADP1740/ADP1741 allow an external soft start capacitor to be connected to program the start-up. The ADP1740/ADP1741 are available in a 16-lead, 4 mm x 4 mm LFCSP, making them very compact solutions while providing excellent thermal performance for applications requiring up to 2 A of output current in a small, low profile footprint. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. 07081-001 ADP1740/ADP1741 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Typical Application Circuits............................................................ 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Preliminary Technical Data Absolute Maximum Ratings ............................................................5 Thermal Resistance .......................................................................5 ESD Caution...................................................................................5 Pin Configurations and Function Descriptions ............................6 Rev. PrA | Page 2 of 6 Preliminary Technical Data SPECIFICATIONS ADP1740/ADP1741 VIN = (VOUT + 0.4 V) or 1.8 V (whichever is greater), IOUT = 10 mA, CIN = COUT = 4.7 F, TA = 25C, unless otherwise noted. Table 1. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Symbol VIN IGND Test Conditions TJ = -40C to +125C IOUT = 0 mA IOUT = 100 mA IOUT = 100 mA, TJ = -40C to +125C IOUT = 2 A IOUT = 2 A, TJ = -40C to +125C EN = GND EN = GND, TJ = -40C to +125C IOUT = 10 mA IOUT = 1 mA to 2 A 1 mA < IOUT < 2 A, TJ = -40C to +125C IOUT = 10 mA IOUT = 1 mA to 2 A 1 mA < IOUT < 2 A, TJ = -40C to +125C VIN = (VOUT + 0.4 V) to 3.6 V, TJ = -40C to +125C IOUT = 10 mA to 2 A, TJ = -40C to +125C IOUT = 100 mA, VOUT 1.8 V IOUT = 100 mA, VOUT 1.8 V, TJ = -40C to +125C IOUT = 2 A, VOUT 1.8 V IOUT = 2 A, VOUT 1.8 V, TJ = -40C to +125C CSS = 10 nF, IOUT = 10 mA ILIMIT TSSD TSSD-HYS PGHIGH PGLOW TJ rising TBD Min 1.6 Typ 45 500 TBD 1.3 1 TBD 3 30 +1 +1.5 +2.5 0.758 0.761 0.769 +0.1 TBD 15 40 200 350 4.8 3 150 15 1.0 0.4 TBD Max 3.6 Unit V A A A mA mA A A % % % V V V %/V %/mA mV mV mV mV ms A C C V V ms SHUTDOWN CURRENT OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy (ADP1740) Adjustable Output Voltage Accuracy (ADP1741)1 LINE REGULATION LOAD REGULATION2 DROPOUT VOLTAGE3 IGND-SD VOUT VOUT VOUT/VIN VOUT/IOUT VDROPOUT -1 -1.5 -2.5 0.743 0.739 0.731 -0.1 0.75 START-UP TIME4 ADP1740 and ADP1741 CURRENT LIMIT THRESHOLD5 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis PG OUTPUT LOGIC LEVEL PG Output Logic High PG Output Logic Low PG Output Delay from EN Transition Low to High PG OUTPUT THRESHOLD PG Threshold, Output Voltage Falling PG Threshold, Output Voltage Rising EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current SOFT START INPUT Soft Start Current ADJ INPUT BIAS CURRENT (ADP1741) SENSE INPUT BIAS CURRENT OUTPUT NOISE tSTART-UP TBD 1.6 V VIN 3.6 V, IOH < 1 A 1.6 V VIN 3.6 V, IOL <2 mA 1.6 V VIN 3.6 V, CSS = 10 nF PGFALL PGRISE VIH VIL VI-LEAKAGE ISS ADJI-BIAS SNSI-BIAS OUTNOISE 1.6 V VIN 3.6 V 1.6 V VIN 3.6 V 1.6 V VIN 3.6 V 1.6 V VIN 3.6 V EN = IN or GND 1.6 V VIN 3.6 V 1.6 V VIN 3.6 V 1.6 V VIN 3.6 V 10 Hz to 100 kHz, VOUT = 0.75 V 10 Hz to 100 kHz, VOUT = 2.5V 1.0 -10 -7 % % V V A A nA A V rms V rms 0.1 TBD 1 30 10 40 80 0.4 1 TBD 100 Rev. PrA | Page 3 of 6 ADP1740/ADP1741 Parameter POWER SUPPLY REJECTION RATIO Symbol PSRR Test Conditions 1 kHz, VOUT = 0.75 V, IOUT = 10 mA 1 kHz, VOUT = 2.5 V, IOUT = 10 mA 10 kHz, VOUT = 0.75 V, IOUT = 10 mA 10 kHz, VOUT = 2.5 V, IOUT = 10 mA Preliminary Technical Data Min Typ 70 60 TBD TBD Max Unit dB dB dB dB 1 Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of resistors used. Based on an end-point calculation using 10 mA and 2 A loads. 3 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 1.6 V. 4 Start-up time is defined as the time between the rising edge of EN to OUT being at 95% of its nominal value. 5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. 2 Rev. PrA | Page 4 of 6 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Parameter IN to GND OUT to GND EN to GND SS to GND PG to GND SENSE/ADJ to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating -0.3 V to +3.6 V -0.3 V to IN -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V -65C to +150C -40C to +125C JEDEC J-STD-020 ADP1740/ADP1741 THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 16-Lead LFCSP with Exposed Pad JA 38 Unit C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. PrA | Page 5 of 6 ADP1740/ADP1741 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 13 OUT 14 OUT Preliminary Technical Data 13 OUT 14 OUT 16 IN 15 IN 16 IN 12 OUT 11 OUT 10 OUT 9 SENSE IN 1 IN 2 IN 3 EN 4 PIN 1 INDICATOR IN 1 IN 2 IN 3 EN 4 PIN 1 INDICATOR 15 IN 12 OUT 11 OUT 10 OUT 9 ADJ ADP1740 TOP VIEW (Not to Scale) ADP1741 TOP VIEW (Not to Scale) PG 5 NC 8 SS 7 GND 6 PG 5 07081-003 GND 6 NC 8 SS 7 NC = NO CONNECT NC = NO CONNECT Figure 3. ADP1740 Pin Configuration Figure 4. ADP1741 Pin Configuration Table 4. Pin Function Descriptions ADP1740 1, 2, 3, 15, 16 4 5 Pin No. ADP1741 1, 2, 3, 15, 16 4 5 Mnemonic IN EN PG Description Regulator Input Supply. Bypass IN to GND with a 4.7 F or greater capacitor. Note that all five pins must be connected to source Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to IN. Power Good. This open-drain output requires an external pull-up resistor to IN. If part is in shutdown, current limit, thermal shutdown, or falls below 90% of the nominal output voltage, PG immediately transitions low. Ground. Soft Start. A capacitor connected to this pin determines the soft start time. Not connected. No internal connection Sense. Measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. Adjust. A resistor divider from OUT to ADJ sets the output voltage. Regulated Output Voltage. Bypass OUT to GND with a 4.7 F or greater capacitor. Note that all five pins must be connected to load Exposed pad on the bottom of the LFCSP package. EP enhances thermal performance and is electrically connected to GND inside the package. It is recommended to connect EP to the ground plane on the board. 6 7 8 9 6 7 8 N/A GND SS NC SENSE N/A 10, 11, 12, 13, 14 EP 9 10, 11, 12, 13, 14 EP ADJ OUT (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07081-0-11/07(PrA) Rev. PrA | Page 6 of 6 07081-004 |
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